What is Transistor Transistor Logic | TTL

What is Transistor Transistor Logic ? | TTL

Due to limited speed, DTL is now out of use area (obsolete) and in its place another logic family Transistor Transistor Logic (TTL) is widely used. The main reason for the slow speed in DTL is the slow removal of stored base charge at the base of the output transistor. Click Here to read this article in Hindi.

The 7400 series of the TTL family was introduced in 1964 by Texas Instruments. Many types of SSI and MSI chips are available in this TTL range, through which almost all types of digital circuits can be made.

Totempole ‘AND’ gate

A TTL NAND gate is shown in the figure. In this circuit, instead of the input diode used in DTL circuits, a multiple emitter configuration is used, due to which high switching speed is achieved. The multiple emitter system is a specialty of the TTL 7400 series.

transistor transistor logic
In the circuit shown in the figure, each emitter of transistor T1 acts as a diode, so transistor T1 and the 4K Ohm resistor act as a 2 input NAND gate. The output stage of a TTL NAND gate is often called a totem-pole stage because the three components of the output part, an NPN transistor and a diode D, are connected in series with each other. This type of output stage is characteristic of TTL devices. In the totem-pole output stage, either one of the transistors T3 or T4 must be ON. When T3 is ‘ON’ the output is HIGH and when T4 is ‘ON’ the output is LOW.

TTL ‘NAND’ Gate Operation | Operation of TTL ‘NAND’ Gate

When both inputs A and B are HIGH (logic 1), no emitter current flows through transistor T1 but its base-collector junction is in forward bias, so it supplies current to the base of transistor T2, resulting in transistor The base of T4 receives current. Hence T4 will conduct and output will be obtained. Note that the collector of T2 will be LOW and T3 will be cut off. As soon as T4 reaches the saturation condition, its output will be LOW (0) because in saturation the collector voltage of T4 is almost equal to the emitter voltage.

When input A or B is LOW (logic 0), base emitter current will flow through T1 and transistor T2 will be cut off as it is grounded. Hence the collector of transistor T2 will become HIGH and T3 will conduct and T4 will be cut-off. Thus again an output will be obtained. Note that the collector of T2 will go HIGH (roughly equivalent to Vcc). The value of potential at point X will be slightly less than Vcc (Vcc – Voltage drop at 100 ohm, T3, and diode D). Since all these voltage drops are very small, the output at point X will be HIG logic 1 ). Thus, the following type of output is obtained from TTL NAND gate in both cases.

1 1 0
0 1 1
1 0 1
0 0 1
  • (i) When both the inputs are HIGH then the output is LOW.
  • (ii) When any of the inputs is LOW, the output is HIGH.

The function of diode D in the circuit is to prevent both transistors T3 and T4 from being ON simultaneously. Because if both are ON then it will create a low impedance path to the supply due to which excessive current will flow and large noise, spikes will be generated in the output

TTL Parameters | Parameters of Transistor Transistor Logic

Fan Out 10
Noise margin 0.4V
Propagation delay 7-10nsec
Power Dissipation 10 mW
Power Supply Voltage +5V

TTL properties

Multiple Emitter Transistor replaces diodes, resistors and transistors combined in other logic circuits. Thus, the size of the device becomes small, which reduces the cost and other functions can also be designed on the IC chip. Other advantages of TTL, apart from low cost, are high operating speed and high fan out.

Wired – AND TTL gate

In wired-AND operation the outputs of some gates are tied together. This combination gives an AND operation and an additional logic function is available. In the figure, suppose the output X of gate-1 is low, then whatever the output Y of gate-2 is, the output Vo will be ‘LOW’. Only, Vo will be high when both X and Y outputs are HIGH. This is an AND operation. Thus, the output Vo = X.Y of the circuit shown in the figure.

Transistor Transistor logic

Open Collector TTL NAND gate

Totem-pole output transistors were often used in the standard TTL family to improve switching speed. In this type of circuit, the lower transistor (T4) provides active pull-down and the upper transistor (T3) provides active pull-up. In both the cases an active device i.e. transistor charges or discharges the capacitor connected at the output which in effect improves the switching speed.

But a serious drawback of Totem-Pole output is that more than one rated output cannot be connected in parallel (Wired-AND). If two or more TTL outputs are connected together and one output is HIGH and the other is LOW then it will almost become like a short circuit and the power dissipation will be very high. But Wired-AND systems become very important in situations where the outputs of multiple TTL devices are to be ANDed. For example, if the outputs of 20 TTL devices need to be ANDed, then a 20-input AND gate will be required if totem-pole devices are used.

open collector ttl gate

To solve the above problem, TTL gate of Open Collector Output was designed. In this gate, only the lower transistor (T4) of the Totem Pole pair is used. The open collector TTL gate is shown in the figure. It is clear from the circuit that the collector of transistor T4 is open. This type of gate will not work properly unless a pull up resistor is connected to the output. The main advantage of open collector gates is that they can be wired together with a common pull-up resistor, so an AND gate is not required. In the figure the outputs of the 3 NAND gates are connected to +5V with the help of a pull-up resistor R.


When any one or all the transistors are saturated then the value of the output voltage becomes low. The only way to get a HIGH output is to have all transistors cut off then the pull-up resistor will pull the output voltage to ‘HIGH’. In other words, wiring the output of open collector devices to a common pull-up resistor automatically results in ANDing. This is called Wired-AND.

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